In the semiconductor industry, NAND flash memory device development is aimed at increasing bit density while at the same time reducing bit cost. Recently, there has been an increase in interest in the use of vertical NAND flash memory cell arrays using terabit cell array transistor (TCAT) technology because of the technology's ability to utilize various advantages related to its metal gate silicon-oxide-nitride-oxide silicon (SONOS) cell structure. Such advantages include faster erase speed, wider Vth margin, and improved retention characteristics. With the SONOS structure, there can be more than 20 layers alternating between oxide and nitride in each vertical NAND stack, and, as a result, etching or stripping processes following word/line (W/L) cut etch can be very difficult due to the high aspect ratio (HAR) trenches that exist. To address this problem, new mask materials have been developed. One such group of new masking materials is doped amorphous carbon (DaC) films. However, with traditional strip processes, the mask removal rate of the DaC films has been less than about 500 Ångströms/minute, which is a removal rate that is much lower than the removal rate that can be reached with conventional amorphous carbon film using traditional strip processes.
As such, in order to make the use of DaC mask materials economically feasible, a need exists for much higher removal rates of the DaC than are currently available. A system and method that can preserve the critical dimensions (CD) and vertical profile of the trenches formed would be useful. A system and method that can reduce the loss of silicon nitride (SiN) and silicon oxide (SiOx) would be particularly useful.